A Low Power Hybrid DCO Using Three Transistor (3-T) XNOR Gate, CMOS and Pseudo-NMOS Inverter

Manju Bagri; Manoj Kumar; Ramnish Kumar

doi:10.34256/ijcci2515

Manju Bagri Department of ECE, Guru Jambheshwar University of Science and Technology, HISAR, Haryana, 125001, India
Manoj Kumar Department of ECE, National Institute of Technology Delhi, Delhi-110036, India
Ramnish Kumar Department of ECE, Guru Jambheshwar University of Science and Technology, HISAR, Haryana, 125001, India

Keywords: Hybrid Digitally Controlled Oscillator, MOS varactor, Phase noise, Delay stage, Pseudo-NMOS inverter

Abstract

This research article presents a comprehensive investigation of three-bit hybrid-digitally controlled ring oscillator (HDCRO) implemented with TMSC 90nm CMOS technology. The hybrid circuit HDCRO comprises of three distinct delay stages, namely XNOR-based inverter, a CMOS inverter, and a Pseudo-NMOS inverter, all of which have been designed utilizing an inversion MOS varactor (IMOS). Furthermore, the investigation explores the output frequency variation in the load element of the HDCRO by adjusting the capacitance of the digitally controlled MOS varactors. This frequency variation occurs as a result of changing the digital control bits of the MOS varactors at a supply voltage of 0.7 V. The proposed HDCRO demonstrates an oscillation frequency range of 2.558 GHz to 2.649 GHz, with power consumption varying from 3.638 mW to 1.046 mW, and phase noise from -68.070 dB@1 MHz to -67.654 dB@1 MHz relative to the central oscillation frequency. Moreover, by applying a supply voltage variation between 0.5 V and 1 V, a wider frequency tuning range of 1.238 GHz to 4.438 GHz is achieved. This extended tuning range exhibits power consumption variation from 2.785 µW to 54.66 mW, and phase noise from -68.812 dB@1 MHz to -65.445 dB@1 MHz relative to the central oscillation frequency. In summary, this study presents a novel HDCRO architecture that demonstrates excellent performance in terms of frequency range, power consumption and phase noise. The proposed design offers advantages of high speed, low-power and good frequency range; thus has a promising prospect of application in high-performance integrated circuits.

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