Energy-Saving Triggering Series Low-Power, High-Performance Locking Systems for Element Design
Pseudo NMOS
Abstract
Flip-flops represent a significant source of power dissipation within a system. The clocking system itself comprises sequential components, such as latches and flip-flops, alongside the network that delivers clock signals. The pseudo-NMOS technology, split path, and clock tree sharing schemes are employed to propose a positive edge triggering flip-flop that is designed for both speed and power efficiency. The flip-flop's latching section's floating node instability and inadequate circuit energy loss are solved via pseudo NMOS and split path approaches, respectively. By enabling the latching part of the flip-flop to share the clock provision network for gathering the data D, the clock tree sharing technique reduces the D-Q delay and the overall number of transistors required to construct the clock provision network. Cutting back on the number of clocked loads is one method that reduces dynamic power dissipation and switching activity. The flip-flop’s latching part is made using this process in the suggested design. This study evaluates the performance of a flip-flop circuit modeled using 0.12 nm CMOS process technology. According to the simulation comparison, the suggested register element design improves The power delay product increased from 56.86th% to 71.26th%, the energy delay product rose from 77.86th% to 82.4th%, and the power energy product (PEP) escalated from 56.22th% to 81.22th%. It conserves between 7.06th% and 32.83rd% of energy.
Downloads
Metrics
References
Zhao, P., McNeely, J., Kuang, W., Wang, N., Wang, Z. (2010). Design of sequential elements for low power clocking system. IEEE Transactions on very large scale integration (VLSI) systems, 19 (2011), 914 – 918. https://doi.org/10.1109/TFUZZ.2011.2150757
Kawaguchi, H., & Sakurai, T. (2002). A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE journal of solid-state circuits, 33(5), 807-811. https://doi.org/10.1109/4.668997
Johnson, T.A., Kourtev, I.S. (2011) a single Latch, high-speed double-edge triggered flip-flop (DETFF), in proc. IEEE International Conference on Electronics, Circuits and Systems, 189-192. https://doi.org/10.1109/ICECS.2001.957712
Kim, C., Kang, S.M., (2002), A low-swing clock double edge-triggered flip-flop, IEEE J. Solid-State Circuits, 37, 648-652. https://doi.org/10.1109/4.997859
Gerosa, G., Gary, S., Dietz, C., Pham, D., Hoover, K., Alvarez, J., Sanchez, H., Ippolito, P., Ngo, T., Litch, S. and Eno, J., 1994. A 2.2 w, 80 mhz superscalar risc microprocessor. IEEE Journal of Solid-State Circuits, 29(12), 1440-1454. https://doi.org/10.1109/4.340417
Yuan, J., Svensson, C. (2002). High-speed CMOS circuit technique. IEEE journal of solid-state circuits, 24(1), 62-70. https://doi.org/10.1109/4.16303
Nikolic, B., Oklobdzija, V. G., Stojanovic, V., Jia, W., Chiu, J. K. S., & Leung, M. M. T. (2000). Improved sense-amplifier-based flip-flop: Design and measurements. IEEE Journal of Solid-State Circuits, 35(6), 876-884. https://doi.org/10.1109/4.845191
Strollo, A. G., De Caro, D., Napoli, E., & Petra, N. (2005). A novel high-speed sense-amplifier-based flip-flop. IEEE transactions on very large scale integration (VLSI) systems, 13(11), 1266-1274. https://doi.org/10.1109/TVLSI.2005.859586
Partovi, H., Burd, R., Salim, U., Weber, F., DiGregorio, L., & Draper, D. (1996, February). Flow-through latch and edge-triggered flip-flop hybrid elements. In 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC, and IEEE. 138-139. https://doi.org/10.1109/ISSCC.1996.488543
Hwang, Y.T., Lin, J.F., Sheu, M.H. (2011). Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme. IEEE transactions on very large scale integration systems, 20(2), 361-366. https://doi.org/10.1109/TVLSI.2010.2096483
Nedovic, N., Oklobdzija, V.G. (2005). Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(5), 577-590. https://doi.org/10.1109/TVLSI.2005.844302
Hirata, A., Nakanishi, K., Nozoe, M., Miyoshi, A. (2005) The cross charge-control flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs’, In Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 306–307. https://doi.org/10.1109/VLSIC.2005.1469392
Klass, F., Amir, C., Das, A., Aingaran, K., Truong, C., Wang, R., Mehta, A., Heald, R. and Yee, G.(1999) A New Family of Semi dynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors. IEEE Journal of Solid-State Circuits, 34(5), 712-716. https://doi.org/10.1109/4.760383
Teh, C.K., Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y. (2007). Conditional data mapping flip-flops for low-power and high-performance systems. IEEE Transactions on very large scale integration (VLSI) systems, 14(12), 1379-1383. https://doi.org/10.1109/TVLSI.2006.887833
Nagarajan, P., Saravanan, R., Thirumurugan, P. (2014). Design of register element for low power clocking system. Information: an international Interdisciplinary journal, 17(6), 2903-2913.
Absel, K., Manuel, L., Kavitha, R.K. (2012). Low-power dual dynamic node pulsed hybrid flip-flop featuring efficient embedded logic. IEEE transactions on very large scale integration (vlsi) systems, 21(9), 1693-1704. https://doi.org/10.1109/TVLSI.2012.2213280
John, P., Uyemura (2005). CMOS logic circuit design, Springer International edition.
Rabaey, J.M, Pedram, M. (1996). Low Power Design Methodologies. Springer Science & Business Media, 366.
Hodges, D., Jackson, H., & Saleh, R. (2003). Analysis and design of digital integrated circuits. McGraw-Hill, Inc.
Gonzalez, R., Gorden, B.M., Horowitz, M. (1997). Supply and Threshold Voltage Scaling for Low Power CMOS’, IEEE J. Solid state circuits, 32(8),1210-1216. https://doi.org/10.1109/4.604077
Sengupta, D., Saleh, R. (2005). Power-delay metrics revisited for 90 nm CMOS technology. In Sixth international symposium on quality electronic design (isqed'05), IEEE, 291-296.
Copyright (c) 2025 Dhilipkumar P
This work is licensed under a Creative Commons Attribution 4.0 International License.
Views: Abstract : 52 | PDF : 33
Plum Analytics
.png){kind=logo}
.png)
.png)
.png)
